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M24C16, M24C08 M24C04, M24C02, M24C01
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial IC Bus EEPROM
FEATURES SUMMARY

Two-Wire IC Serial Interface Supports 400kHz Protocol Single Supply Voltage: - 2.5 to 5.5V for M24Cxx-W - 1.8 to 5.5V for M24Cxx-R Write Control Input BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Protection More than 1 Million Erase/Write Cycles More than 40-Year Data Retention Packages - ECOPACK(R) (RoHS compliant)
Figure 1. Packages
8 1
PDIP8 (BN)
8 1
Table 1. Product List
Reference M24C16 M24C16-R M24C08-W M24C08 M24C08-R M24C04-W M24C04 M24C04-R M24C02-W M24C02 M24C02-R M24C01-W M24C01 M24C01-R Part Number M24C16-W
SO8 (MN) 150 mil width
TSSOP8 (DW) 169 mil width
TSSOP8 (DS) 3x3mm body size (MSOP)
UFDFPN8 (MB) 2x3mm (MLP)
October 2005
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M24C16, M24C08, M24C04, M24C02, M24C01
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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M24C16, M24C08, M24C04, M24C02, M24C01
SUMMARY DESCRIPTION
These IC-compatible electrically erasable programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8 (M24C16, M24C08, M24C04, M24C02 and M24C01). In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. Logic Diagram scribed in Table 3.), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Table 2. Signal Names
E0, E1, E2 SDA Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground
VCC
SCL WC
3 E0-E2 SCL WC M24Cxx SDA
VCC VSS
VSS
AI02033
IC uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the IC bus definition. The device behaves as a slave in the IC protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and Read/Write bit (RW) (as deFigure 3. 8-Pin Package Connections (Top View)
Device internal reset In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any instructions until the VCC has reached the Power On Reset threshold voltage (this threshold is lower than the VCC min. operating voltage defined in DC and AC PARAMETERS). When VCC has passed over the POR threshold, the device is reset and is in Standby Power mode. At Power-down (continuous decay of VCC), as soon as VCC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it. Prior to selecting and issuing instructions to the memory, a valid and stable VCC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
M24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb NC / NC / NC / E0 / E0 NC / NC / E1 / E1 / E1 NC / E2 / E2 / E2 / E2 VSS 1 2 3 4 8 7 6 5 VCC WC SCL SDA
AI02034E
Note: 1. NC = Not Connected 2. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.
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M24C16, M24C08, M24C04, M24C02, M24C01
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VCC. (Figure 5. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA). This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5. indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2). These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7bit Device Select Code. These inputs must be tied to VCC or VSS, to establish the Device Select Code as shown in Figure 4. Figure 4. Device Select Code
VCC VCC
M24Cxx Ei
M24Cxx Ei
VSS
VSS
Ai11650
Write Control (WC). This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.
Figure 5. Maximum RP Value versus Bus Parasitic Capacitance (C) for an IC Bus
VCC 20 Maximum RP value (k) 16 RP 12 8 4 0 10 100 C (pF)
AI01665b
RP
SDA MASTER fc = 100kHz fc = 400kHz SCL C
C 1000
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. IC Bus Protocol
SCL
SDA SDA Input SDA Change
START Condition
STOP Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP Condition
AI00792B
Table 3. Device Select Code
Device Type Identifier1 b7 M24C01 Select Code M24C02 Select Code M24C04 Select Code M24C08 Select Code M24C16 Select Code 1 1 1 1 1 b6 0 0 0 0 0 b5 1 1 1 1 1 b4 0 0 0 0 0 b3 E2 E2 E2 E2 A10 Chip Enable2,3 b2 E1 E1 E1 A9 A9 b1 E0 E0 A8 A8 A8 RW b0 RW RW RW RW RW
Note: 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. 3. A10, A9 and A8 represent most significant bits of the address.
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M24C16, M24C08, M24C04, M24C02, M24C01
DEVICE OPERATION
The device supports the IC protocol. This is summarized in Figure 6.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24Cxx device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Table 4. Operating Modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3. (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b. Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. However, those devices with larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not available for devices that need to use address line A9, and E2 is not available for devices that need to use address line A10 (see Figure 3. and Table 3. for details). Using the E0, E1 and E2 inputs, up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can be connected to one IC bus. In each case, and in the hybrid cases, this gives a total memory capacity of 16 Kbits, 2 KBytes (except where M24C01 devices are used). The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.
RW bit 1 0
WC 1 X X
Bytes 1 1
Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address reSTART, Device Select, RW = 1
X X VIL VIL 1 1 16
1 0 0
Similar to Current or Random Address Read START, Device Select, RW = 0 START, Device Select, RW = 0
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure 7. Write Mode Sequences with WC=1 (data write inhibited)
WC ACK Byte Write START DEV SEL R/W ACK NO ACK DATA IN STOP ACK NO ACK DATA IN 1
BYTE ADDR
WC ACK Page Write START DEV SEL R/W NO ACK DATA IN 3
BYTE ADDR
DATA IN 2
WC (cont'd) NO ACK Page Write (cont'd) NO ACK
DATA IN N STOP
AI02803C
Write Operations Following a Start condition the bus master sends a Device Select Code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8., and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the device does not respond to any requests. Byte Write After the Device Select code and the address byte, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High (during the period from
the Start condition until the end of the address byte), the device replies to the data byte with NoAck, as shown in Figure 7., and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8.. Page Write The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as `rollover' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed location is Write-protected, by Write Control (WC) being driven High (during the period from the Start
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M24C16, M24C08, M24C04, M24C02, M24C01
condition until the end of the address byte), the device replies to the data bytes with NoAck, as shown in Figure 7., and the locations are not modified. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.
Figure 8. Write Mode Sequences with WC=0 (data write enabled)
WC ACK BYTE WRITE START DEV SEL R/W ACK DATA IN STOP ACK DATA IN 1 ACK DATA IN 2 ACK
BYTE ADDR
WC ACK PAGE WRITE START DEV SEL R/W ACK DATA IN 3
BYTE ADDR
WC (cont'd)
ACK PAGE WRITE (cont'd) DATA IN N
ACK
STOP
AI02804B
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure 9. Write Cycle Polling Flowchart using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Address and Receive ACK
STOP
NO
START Condition
YES
DATA for the WRITE Operation
DEVICE SELECT with RW = 1
Continue the WRITE Operation
Continue the Random READ Operation
AI01847C
Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 13. and Table 14., but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9., is:
- -
-
Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure 10. Read Mode Sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK DEV SEL * START R/W
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK
NO ACK DATA OUT STOP NO ACK ACK
AI01942
BYTE ADDR
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical.
Read Operations Read operations are performed independently of the state of the Write Control (WC) signal. The device has an internal address counter which is incremented each time a byte is read. Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10.) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the ad-
dressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10., without acknowledging the byte.
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M24C16, M24C08, M24C04, M24C02, M24C01
Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10.. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode.
INITIAL DELIVERY STATE
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
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M24C16, M24C08, M24C04, M24C02, M24C01
MAXIMUM RATING
Stressing the device outside the ratings listed in Table 5. may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of Table 5. Absolute Maximum Ratings
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering 1 Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 -0.50 -0.50 -4000
ECOPACK(R)
this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Min. -40 -65
Max. 125 150
Unit C C C
6.5 6.5 4000
V V V
Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500, R2=500)
7191395 specification, and
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M24C16, M24C08, M24C04, M24C02, M24C01
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 6. Operating Conditions (M24Cxx-W)
Symbol VCC TA Ambient Operating Temperature (Device Grade 3) -40 125 C Supply Voltage Ambient Operating Temperature (Device Grade 6) Parameter Min. 2.5 -40 Max. 5.5 85 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 7. Operating Conditions (M24Cxx-R)
Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 8. DC Characteristics (M24Cxx-W, Device Grade 6)
Symbol ILI ILO ICC Parameter Input Leakage Current (SCL, SDA, E0, E1,and E2) Output Leakage Current Supply Current VCC =2.5V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 5 V Stand-by Supply Current VIN = VSS or VCC , VCC = 2.5 V Input Low Voltage (1) Input High Voltage (1) Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V -0.45 0.7VCC 0.5 0.3VCC VCC+1 0.4 A V V V 1 1 mA A Test Condition (in addition to those in Table 6.) VIN = VSS or VCC VOUT = VSS or VCC, SDA in Hi-Z VCC=5V, fc=400kHz (rise/fall time < 30ns) Min. Max. 2 2 2 Unit A A mA
ICC1 VIL VIH VOL
Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.
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M24C16, M24C08, M24C04, M24C02, M24C01
Table 9. DC Characteristics (M24Cxx-W, Device Grade 3)
Symbol ILI ILO ICC Parameter Input Leakage Current (SCL, SDA, E0, E1,and E2) Output Leakage Current Test Condition (in addition to those in Table 6.) VIN = VSS or VCC VOUT = VSS or VCC, SDA in Hi-Z VCC=5V, fC=400kHz (rise/fall time < 30ns) Supply Current VCC =2.5V, fC=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 5 V VIN = VSS or VCC , VCC = 2.5 V Input Low Voltage (1) Input High Voltage (1) Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V -0.45 0.7VCC Min. Max. 2 2 3 3 5 2 0.3VCC VCC+1 0.4 Unit A A mA mA A A V V V
ICC1 VIL VIH VOL
Stand-by Supply Current
Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.
Table 10. DC Characteristics (M24Cxx-R)
Symbol ILI ILO ICC ICC1 VIL VIH VOL Parameter Input Leakage Current (SCL, SDA, E0, E1,and E2) Output Leakage Current Supply Current Stand-by Supply Current Input Low Voltage (1) Input High Voltage (1) Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V Test Condition (in addition to those in Table 7.) VIN = VSS or VCC VOUT = VSS or VCC, SDA in Hi-Z VCC =1.8V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 1.8 V 2.5 V VCC 1.8 V VCC < 2.5 V -0.45 -0.45 0.7VCC Min. Max. 2 2 0.8 0.3 0.3 VCC 0.25 VCC VCC+1 0.2 Unit A A mA A V V V V
Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.
Table 11. AC Measurement Conditions
Symbol CL Load Capacitance Input Rise and Fall Times Input Levels Input and Output Timing Reference Levels Parameter Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
14/25
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 11. AC Measurement I/O Waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 12. Input Parameters
Symbol CIN CIN ZWCL ZWCH tNS Parameter1,2 Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance WC Input Impedance Pulse width ignored (Input Filter on SCL and SDA) VIN < 0.3 V VIN > 0.7VCC Single glitch 15 500 100 Test Condition Min. Max. 8 6 70 Unit pF pF k k ns
Note: 1. TA = 25C, f = 400kHz 2. Sampled only, not 100% tested.
15/25
M24C16, M24C08, M24C04, M24C02, M24C01
Table 13. AC Characteristics (M24Cxx-W)
Test conditions specified in Table 6. and Table 11. Symbol fC tCHCL tCLCH tDL1DL2 2 tDXCX tCLDX tCLQX tCLQV tCHDX
3 1
Alt. fSCL tHIGH tLOW tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Clock Frequency
Parameter
Min.
Max. 400
Unit kHz ns ns
Clock Pulse Width High Clock Pulse Width Low SDA Fall Time Data In Set Up Time Data In Hold Time Data Out Hold Time Clock Low to Next Data Valid (Access Time) Start Condition Set Up Time Start Condition Hold Time Stop Condition Set Up Time Time between Stop Condition and Next Start Condition Write Time
600 1300 20 100 0 200 200 600 600 600 1300 5 900 300
ns ns ns ns ns ns ns ns ns ms
tDLCL tCHDH tDHDL tW
4
Note: 1. 2. 3. 4.
For a reSTART condition, or following a Write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. Previous devices bearing the process letter "L" in the package marking guarantee a maximum write time of 10ms. For more information about these devices and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/ EE/0061 and 0062 (PCEE0061 and PCEE0062).
Table 14. AC Characteristics (M24Cxx-R)
Test conditions specified in Table 7. and Table 10. Symbol fC tCHCL tCLCH tDL1DL2 tDXCX tCLDX tCLQX tCLQV 3 tCHDX 1 tDLCL tCHDH tDHDL tW
Note: 1. 2. 3. 4.
2
Alt. fSCL tHIGH tLOW tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Clock Frequency
Parameter
Min. 4
Max. 4 400
Unit kHz ns ns
Clock Pulse Width High Clock Pulse Width Low SDA Fall Time Data In Set Up Time Data In Hold Time Data Out Hold Time Clock Low to Next Data Valid (Access Time) Start Condition Set Up Time Start Condition Hold Time Stop Condition Set Up Time Time between Stop Condition and Next Start Condition Write Time
600 1300 20 100 0 200 200 600 600 600 1300 10 900 300
ns ns ns ns ns ns ns ns ns ms
For a reSTART condition, or following a Write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. This is preliminary information.
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure 12. AC Waveforms
tCHCL
tCLCH
SCL tDLCL SDA In tCHDX START Condition SDA Input tCLDX SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition
SCL
SDA In tCHDH STOP Condition tW Write Cycle tCHDX START Condition
SCL tCLQV SDA Out Data Valid tCLQX
AI00795C
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M24C16, M24C08, M24C04, M24C02, M24C01
PACKAGE MECHANICAL
Figure 13. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
b2 A2 A1 b e A L
E
c eA eB
D
8
E1
1 PDIP-B
Note: Drawing is not to scale.
Table 15. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm Symb. Typ. A A1 A2 b b2 c D E E1 e eA eB L 3.30 2.92 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 - - 4.95 0.56 1.78 0.36 10.16 8.26 7.11 - - 10.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 Min. Max. 5.33 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 - - 0.195 0.022 0.070 0.014 0.400 0.325 0.280 - - 0.430 0.150 Typ. Min. Max. 0.210 inches
18/25
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 14. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: Drawing is not to scale.
Table 16. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
19/25
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 15. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Outline
D L3
e
b L1
E
E2
L A D2 ddd A1
UFDFPN-01
Note: 1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 17. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Data
mm Symbol Typ. A A1 b D D2 ddd E E2 e L L1 L3 N 8 0.30 8 0.50 0.45 3.00 0.15 - 0.40 0.25 - 0.50 0.15 0.012 0.020 0.018 0.25 2.00 1.55 1.65 0.05 0.118 0.006 - 0.016 0.010 - 0.020 0.006 0.55 Min. 0.50 0.00 0.20 Max. 0.60 0.05 0.30 0.010 0.079 0.061 0.065 0.002 Typ. 0.022 Min. 0.020 0.000 0.008 Max. 0.024 0.002 0.012 inches
20/25
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 16. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
Note: Drawing is not to scale.
Table 18. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm Symbol Typ. A A1 A2 b c CP D e E E1 L L1 3.000 0.650 6.400 4.400 0.600 1.000 0 8 2.900 - 6.200 4.300 0.450 1.000 0.050 0.800 0.190 0.090 Min. Max. 1.200 0.150 1.050 0.300 0.200 0.100 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295 inches
21/25
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 17. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Package Outline
D
8
5 E1 E
c
1
4
A1 A CP b e A2
L L1
TSSOP8BM
Note: Drawing is not to scale.
Table 19. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm Symbol Typ. A A1 A2 b c D E E1 e CP L L1 0.550 0.950 0 6 0.400 3.000 4.900 3.000 0.650 0.850 0.050 0.750 0.250 0.130 2.900 4.650 2.900 - Min. Max. 1.100 0.150 0.950 0.400 0.230 3.100 5.150 3.100 - 0.100 0.700 0.0217 0.0374 0 6 0.0157 0.1181 0.1929 0.1181 0.0256 0.0335 0.0020 0.0295 0.0098 0.0051 0.1142 0.1831 0.1142 - Typ. Min. Max. 0.0433 0.0059 0.0374 0.0157 0.0091 0.1220 0.2028 0.1220 - 0.0039 0.0276 inches
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M24C16, M24C08, M24C04, M24C02, M24C01
PART NUMBERING
Table 20. Ordering Information Scheme
Example: Device Type M24 = I2C serial access EEPROM Device Function 16 = 16 Kbit (2048 x 8) 08 = 8 Kbit (1024 x 8) 04 = 4 Kbit (512 x 8) 02 = 2 Kbit (256 x 8) 01 = 1 Kbit (128 x 8) Operating Voltage W = VCC = 2.5 to 5.5V (400 kHz) R = VCC = 1.8 to 5.5V (400 kHz) Package BN = PDIP8 MN = SO8 (150 mil width) MB = UDFDFPN8 (MLP8) DW = TSSOP8 (169 mil width) DS = TSSOP8 (3x3mm body size, MSOP8) Device Grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Device tested with High Reliability Certified Flow1. Automotive temperature range (-40 to 125 C) Option T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating P or G = ECOPACK(R) (RoHS compliant) Process2 /W or /S = F6SP36%
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Used only for Device Grade 3.
M24C16
-
W DW 3
T
P
/W
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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M24C16, M24C08, M24C04, M24C02, M24C01
REVISION HISTORY
Table 21. Document Revision History
Date 10-Dec-1999 18-Apr-2000 05-May-2000 23-Nov-2000 Version 2.4 2.5 2.6 3.0 Description of Revision TSSOP8 Turned-Die package removed (p 2 and order information) Lead temperature added for TSSOP8 in table 2 Labelling change to Fig-2D, correction of values for `E' and main caption for Tab-13 Extra labelling to Fig-2D SBGA package information removed to an annex document -R range changed to being the -S range, and the new -R range added SBGA package information put back in this document Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated References to PSDIP changed to PDIP and Package Mechanical data updated Wording brought in to line with standard glossary Revision of DC and AC characteristics for the -S series Ball numbers added to the SBGA connections and package mechanical illustrations Specification of Test Condition for Leakage Currents in the DC Characteristics table improved Document reformatted using new template. SBGA5 package removed TSSOP8 (3x3mm body size) package (MSOP8) added. -L voltage range added Document title spelt out more fully. "W"-marked devices with tw=5ms added. -R voltage range upgraded to 400kHz working, and no longer preliminary data. 5V voltage range at temperature range 3 (-xx3) no longer preliminary data. -S voltage range removed. -Wxx3 voltage+temp ranged added as preliminary data. Table of contents, and Pb-free options added. Minor wording changes in Summary Description, Power-On Reset, Memory Addressing, Read Operations. VIL(min) improved to -0.45V. tW(max) value for -R voltage range corrected. MLP package added. Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified. Process identification letter "G" information added. 2.2-5.5V range is removed, and 4.5-5.5V range is now Not for New Design Product List summary table added. AEC-Q100-002 compliance. Device Grade informaton clarified. Updated Device internal reset section, Figure 4., Figure 5., Table 14. and Table 20. Added Ecopack(R) information. Updated tW=5ms for the M24Cxx-W.
19-Feb-2001
3.1
20-Apr-2001 08-Oct-2001 09-Nov-2001 30-Jul-2002 04-Feb-2003 05-May-2003
3.2 3.3 3.4 3.5 3.6 3.7
07-Oct-2003
4.0
17-Mar-2004
5.0
7-Oct-2005
6.0
24/25
M24C16, M24C08, M24C04, M24C02, M24C01
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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